The present invention relates to a semiconductor integrated circuit device and a semiconductor memory system, and particularly to a technique effective for use in devices which need minute or micro and highly-accurately controlled delay signals. This invention also relates to a clock synchronous circuit having quick response and high accuracy and a technique effective for use in a semiconductor integrated circuit device such as a synchronous DRAM (Dynamic Random Access Memory) equipped with the clock synchronous circuit.
The following array oscillator disclosed by ISSCC has been known as an example of a circuit for obtaining a time resolution of a few 10 psec (picoseconds). This type of array oscillator is known as one wherein the same ring oscillators are arranged in large numbers in a column direction and connected in ring form using one inputs with each individual stages as two inputs, and the outputs of the respective stages are respectively supplied to other inputs of adjoining stages, and they are also connected in ring form even in a row direction. Such an oscillator has been described in ISSCC 93/ANALOG TECHNIQUES/PAPER TA7.5, pp. 118-119, 1993 and ISSCC/SESSION 18/MEMORIES WITH SPECIAL ARCHITECTURES/PAPER FP18.5, pp308-309, 1995, and Japanese Published Unexamined Patent Application No. Hei 8-78951.
A clock synchronous circuit excluding a feedback loop like a synchronous mirror delay (SMD) is characterized in that the time (lock time) necessary for synchronization is short as is the case of 2 to 3 cycles. According to this feature, the lock time can be shortened by measuring the cycle of an input clock as the number of stages of delay circuits or coarse delays. The time resolution of this measuring circuit is determined depending on a delay time per stage corresponding to a component of each delay circuit. The time resolution is normally on the order of a delay time corresponding to two stages of CMOS inverters Japanese Published Unexamined Patent Application No. Hei 8-237091 is known as an example of a clock synchronous circuit using such an SMD.
In order to speed up a semiconductor memory such as a dynamic RAM (Random Access Memory) or the like, memory access times as seen from a memory controller for generally controlling plural RAMs are made uniform by making uniform signal transfer delays on a substrate mounted between such RAMs and the memory controller, in other words, in anticipation of the signal propagation delays on the mounted substrate, increasing delay times thereinside when such signal delays are small and decreasing delays thereinside when such signal delays are large, whereby it is possible to easily ensure the time (window) required to allow data capturing occupied in a cycle time and speed up a memory cycle time If semiconductor memories are implemented on a mounting substrate having signal wires or interconnections whose each characteristic impedance is 50xcexa9, at 1 centimeter (cm) intervals, a signal propagation delay time encountered between each individual semiconductor memories becomes about 50 psec. It is therefore necessary to provide delay circuits each having a high-precision time resolution of a few 10 psec inside the respective semiconductor memories with a view toward making uniform the signal transfer delays between the memory controller and the respective semiconductor memories as described above.
The inventors or the like of the present application have discussed the utilization of the above-described array oscillator to implement the delay circuits each having the above-mentioned high-precision time resolution In the array oscillator, however, delay signals having delays equal to each other by the number of respective stages are to be formed for the number of logic stages lying in a row direction. However, in a circuit formed on an actually-available semiconductor substrate, each signal delay encountered in the row direction will not be recognized to have satisfactory linearity, and the signal delay will become fast in one logic stage or slow in another logic stage. Thus, it has been found that even if the principle of the above-described array oscillator is used as it is, the above-mentioned micro and uniform signal delay like a few 10 psec cannot be obtained.
It has been recognized by the inventors that a problem arises in that if it is assumed that minute and uniform signal delays are obtained and logic circuits are disposed on a semiconductor substrate in lattice form along row and column directions, then signal paths for taking out output signals cannot be provided evenly in the cases: where delay signals are respectively outputted from logic circuits disposed inside the lattice form and where delay signals are respectively outputted from logic circuits disposed outside the lattice form.
Since the array oscillator is made up of ring oscillators, a start-up time between its deactivated state and stabilization of its operation is relatively long. It has been thus evident from the discussions of the present inventors that a problem arises in that the formation of a desired signal at high speed falls into difficulties.
A first object of this invention is to provide a semiconductor integrated circuit device provided with a circuit for forming signals each having minute and high-accuracy time resolution. A second object of this invention is to provide a semiconductor integrated circuit device having a delay circuit disposed on a semiconductor substrate with efficiency and capable of forming delay signals each having micro and high-accuracy time resolution. A third object of this invention is to provide a semiconductor memory system capable of implementing the input and output of data at high speed.
A fourth object of this invention is to provide a semiconductor integrated circuit device provided with a circuit for forming signals each having small and high-accuracy time resolution at high speed.
A summary of a typical one of the inventions disclosed according to the first through fourth objects of the inventions of the present application will be described in brief as follows:
There is provided a semiconductor integrated circuit device comprising:
at least one delay circuit including,
M signal lines for receiving a first input signal to successively-delayed M (M=2, 3, 4, . . . )th input signals therein; and
M logic gate circuit groups extending from a first logic gate circuit group corresponding to the first input signal to an Mth logic gate circuit group corresponding to the Mth input signal, and
wherein each individual logic gate circuit groups have N logic gate circuits extending from a first logic gate circuit to an N (N=3, 4, 5, . . . )th logic gate circuit, each logic gate circuit having a first input terminal, a second input terminal and an output terminal, coupling elements are provided between the first and second input terminals of the logic gate circuits respectively,
the first to Nth logic gate circuits in each logic gate circuit group are tandem-connected to the output terminals through the first input terminals respectively,
the M signal lines are connected to the first input terminals of the first logic gate circuits in their corresponding logic gate circuit groups,
first input terminals of L (L=1, 2, 3, . . . )th logic gate circuits in each of the first logic gate circuit group to Mxe2x88x921th logic gate circuit group are connected to second input terminals of Lth logic gate circuits in the next logic gate circuit group,
first input terminals of predetermined logic gate circuits in the Mth logic gate circuit group are connected to second input terminals of predetermined logic gate circuits in the first logic gate circuit group, and
successively-delayed output signals are respectively obtained from the output terminals of a plurality of the Nth logic gate circuits
A summary of another typical one of the inventions disclosed in association with the first to fourth objects of the inventions of the present application will be described in brief as follows:
There is provided a semiconductor integrated circuit device comprising:
at least one delay circuit including,
a plurality of logic gate circuits which are respectively provided with impedance elements for respectively coupling two input signals inputted to first and second input terminals, each impedance element being provided between the first and second input terminals, and respectively form output signals according to the input signals supplied to the first and second input terminals,
the plurality of logic gate circuits being capable of being disposed in lattice form in a first signal transfer direction and a second signal transfer direction, and
wherein the first input terminal of a logic gate circuit KL provided as a Kth other than the first as seen in the first signal transfer direction and disposed in an Lth stage as seen in the second signal transfer direction is supplied with a signal outputted from a logic gate circuit provided as the same Kth as seen in the first signal transfer direction and defined as an Lxe2x88x921th stage as seen in the second signal transfer direction or an input clock signal in the case of the first-stage logic gate circuit, and the second input terminal of the logic gate circuit KL is supplied with an input signal supplied to a first input terminal of a logic gate circuit provided as the immediately preceding Kxe2x88x921th as seen in the first signal transfer direction and defined as the same Lth stage as seen in the second signal transfer direction;
a second input terminal of a logic gate circuit provided as the first as seen in the first signal transfer direction and defined as an Lth as seen in the second signal transfer direction is supplied with an input signal supplied to a first input terminal of a logic gate circuit defined as the final stage as seen in the first signal transfer direction, the input signal being in phase with an input signal supplied to a first input terminal of a logic gate circuit at a stage preceding the final stage as seen in the second signal transfer direction;
the first and second input terminals of the logic gate circuits defined as the first stage as seen in the second signal transfer direction and provided as the first as seen in the first signal transfer direction are respectively supplied with a clock signal through a corresponding input circuit constituting a buffer, and the input clock signals supplied to the first input terminals of the respective logic gate circuits extending from the second to the last as seen in the first signal transfer direction are delayed in order in the first signal transfer direction by the corresponding input circuit constituting the buffer; and
output signals are respectively obtained from output terminals of a plurality of logic gate circuits placed in at least a plural-numbered stage as seen in the second signal transfer direction and arranged in the first signal transfer direction.
A summary of a further typical one of the inventions disclosed in association with the first to fourth objects of the inventions of the present application will be described in brief as follows:
There is provided a semiconductor integrated circuit-device comprising:
a first circuit including a plurality of unit circuits for respectively forming a first input clock signal to successively-delayed M (M=2, 3, 4, . . . )th input clock signals in response to a reference clock signal, the first circuit forming the first to Mth input clock signals within one cycle of the reference clock signal in association with successively different characteristics of circuit elements respectively included in the plurality of unit circuits; and
a second circuit for receiving the first to Mth input clock signals therein and obtaining a plurality of output clock signals successively delayed with delay amounts uniform than respective delay amounts of the first to Mth input clock signals;
wherein the second circuit is a delay circuit having a plurality of logic gate circuits corresponding to M rows and N columns (where N=3, 4, . . . ) and wired so that signals are transmitted in row and column directions of the plurality of logic gate circuits.
A fifth object of this invention is to provide a high-accuracy and quick-response clock synchronous circuit and a semiconductor integrated circuit device using the clock synchronous circuit. A sixth object of this invention is to provide a clock synchronous circuit capable of implementing on-standby less power consumption and high-speed reset with high accuracy and a semiconductor integrated circuit device using the clock synchronous circuit. A seventh object of this invention is to provide a clock synchronous circuit capable of realizing fast response with high accuracy without an increase in circuit scale and a semiconductor integrated circuit device using the clock synchronous circuit. Other objects of this invention or the above and other objects and novel features of this invention will become apparent from the following description of the present specification and the accompanying drawings.
A summary of a typical one of the inventions disclosed in correspondence with the fifth through seventh objects of the inventions of the present application will be described in brief as follows:
A lattice-like delay circuit is configured wherein a first delay circuit or coarse delay for propagating a clock pulse with relatively low time resolution, a first edge detector and a first multiplexer are used to form or create a clock signal delayed by one clock in association with the relatively low time resolution, a second coarse delay having relatively high time resolution, a second edge detector and a second multiplexer are used to correct an error of the first coarse delay, included in the above signal, and a plurality of logic gate means each of which is provided with impedance means for making coupling between two input signals inputted between first and second input terminals as a second delay circuit having high time resolution as the above second coarse delay and each of which produces an output signal obtained by inverting the input signals, are used so as to be placed in lattice form in first and second signal transfer directions. The lattice-like delay circuit is used wherein the respective logic gate means extending from the first to the last as seen in the first signal transfer direction are respectively successively supplied with input clock signals with their delays as seen in the first signal transfer direction, and output signals are obtained from output terminals of the plurality of logic gate means placed in at least the final stage or the immediately preceding stage as seen in the second signal transfer direction and arranged in the first signal transfer direction. The lattice-like delay circuit referred to above is installed in a semiconductor integrated circuit device such as a synchronous DRAM or the like.